BIST for Delay-Faults in Digital High-Speed ICs
نویسنده
چکیده
Testing of high-speed integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a BIST methodology such that high performance devices can be tested on relatively low performance testers. In addition, also a full BIST technique is addressed. Keywords— Delay-Fault Testing, At-Speed Testing, Built-In Self-Testing, Partial BIST, ControlledDelay Flip-flops
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تاریخ انتشار 1999